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TDA7430 tda7431 digitally controlled audio processor with surround sound matrix and voice canceller 1 stereo (4 stereo) input + 1 mixer in- put input attenuation control in 0.5db step voice canceller is available treble middle and bass control three surround modes are avail- able: - music: 4 selectable responses - movie and simulated: 256 selectable responses 2 speaker and 2 record attenu- ators: - 2 independent speakers and 2 independent record control in 1db step for balance facility - availability of loudspeaker equalization fixed by external components - independent mute function all functions programmable via se- rial bus description the TDA7430/7431 are volume tone (bass middle and treble) balance (left/right) processors with voice canceller for quality audio applications in car radio and hi-fi systems. they reproduce surround sound by using pro- grammable phase shifters and a signal matrix. control of all the functions is accomplished by se- rial bus. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are obtained. september 1999 pin connections ordering numbers: TDA7430 (tqfp44) tda7431 (sdip42) sdip42 tqfp44 1 3 2 4 5 6 7 8 9 r_out l_out recout_r nblo recout_l nblin l_in mix r_in 37 36 35 34 33 31 32 30 29 d95au219b 10 11 12 13 14 42 41 40 39 38 lpvc nbrin nbro cref v s 15 16 treble_r treble_l agnd sda addr scl dig_gnd 28 27 26 24 25 23 22 17 18 19 20 21 lp1 hp1 hp2 voutref var_l var_r basso_l basso_r bass_lo ps4 ps3 ps2 ps1 lp bass_li bass_ro bass_ri middle_li middle_lo middle_ro middle_ri 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 var_l rearin rearout hp1 lp1 hp2. bass_li bass_lo basso_r basso_l var_r bass_ro bass_ri middle_lo middle_li middle_ri middle_ro treble_r treble_l agnd sda scl lp ps1 ps2 ps3 v s ps4 cref r_in4 r_in3 r_in2 lpvc l_in4 recout_l recout_r r_out dig_gnd l_out r_in1 mix l_in1 l_in3 l_in2 d95au220b 12 13 14 15 16 ? 1/21
l-in1 rlp1 l-r 0.47 m f supply v s agnd cref treble 18nf middle 2.7k middle-li middle-lo 22nf rm bass bass-li mute d95au221b mute i 2 c bus decoder + latches spkr att rec att treble middle bass 18nf 22nf 2.7k 5.6nf mute spkr att mute rec att scl sda dig gnd r-out recout-r l-out recout-l 22 m f + - + - + rhp1 lp1 hp1 hp2 5.6nf 680nf - + r6 r5 r-in4 0.47 m f 50k ps1 90hz 100nf ps1 rps1 sim movie/ music music off ps2 4khz ps3 400hz ps4 400hz 4.7nf ps2 rps2 22nf ps3 rps3 22nf ps4 rps4 movie/sim mixing amp lpf 9khz effect control mixing amp 1.2nf lp middle-ri middle-ro 31 1 2 3 43 42 41 40 37 39 20 38 44 15 14 11 25 17 16 13 27 22 21 23 24 26 + - + lpf 100k 1 m f 100nf lpvc mix treble-r 79db control 5.6nf treble-l 100nf 5.6k 100nf bass-lo 100nf 100nf 5.6k bass-ri bass-ro 79db control 79db control 2.2 m f basso-r var-r 30k + - + - 2.2 m f basso-l var-l 30k 79db control 10 7 6 8 9 12 18 32 34 19 50k 0.47 m f 50k 0.47 m f 50k 0.47 m f 50k 0.47 m f 50k 0.47 m f 50k 0.47 m f 50k 31.5db control r-in3 r-in2 r-in1 31.5db control l-in2 l-in3 l-in4 2.2 m f 50k rearin rearout 30 29 28 33 35 36 45 mix-in voice on vref off surr off surr rm rb surr rear fix 3band surr rear fix 3band fix var rb fix var the switches position matches the reset condition block diagram (TDA7430) TDA7430 - tda7431 2/21
l-in rlp1 l-r 0.47 m f supply v s agnd cref treble 18nf middle 2.7k middle-li middle-lo 22nf rm bass bass-li mute d95au222c mute i 2 c bus decoder + latches spkr att rec att treble middle bass 18nf 22nf 2.7k 5.6nf mute spkr att mute rec att scl sda dig gnd r-out recout-r l-out recout-l 22 m f 50k + - + - + rhp1 lp1 hp1 hp2 5.6nf 680nf - + r6 r5 r-in 0.47 m f 50k ps1 90hz 100nf ps1 rps1 sim movie/ music music off ps2 4khz ps3 400hz ps4 400hz 4.7nf ps2 rps2 22nf ps3 rps3 22nf ps4 rps4 movie/sim mixing amp lpf 9khz effect control mixing amp 1.2nf lp middle-ri middle-ro 35 678 4321 37 42 24 41 5 19 18 15 30 21 20 17 32 27 26 28 29 31 + - + lpf 100k 1 m f 100nf lpvc mix voutref treble-r 79db control 5.6nf treble-l 100nf 5.6k 100nf bass-lo 100nf 100nf 5.6k bass-ri bass-ro 79db control 79db control 2.2 m f basso-r var-r nb-ra nb-rb nb4 nbrin nbro nb3 30k + - + - 2.2 m f basso-l var-l nb-la nb-lb nb1 nblin nblo nb2 30k 25 addr 79db control 14 11 10 34 33 40 39 12 13 16 22 9 36 38 23 31.5db control 31.5db control mix-in voice on the switches position matches the reset condition vref off surr rb rm rb rear surr 3band fix 3band fix rear surr surr off fix var fix var block diagram (tda7431) TDA7430 - tda7431 3/21
thermal data symbol description value unit r th j-pins thermal resistance junction-pins max. 85 c/w quick reference data symbol parameter min. typ. max. unit v s supply voltage 7 9 10.2 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db treble control (2db step) -14 +14 db middle control (2db step) -14 +14 db bass control (2db step) -14 +14 db balance control 1db step (l ch, r ch ) -79 0 db mute attenuation 100 db absolute maximum ratings symbol parameter value unit v s operating supply voltage 11 v t amb operating ambient temperature -10 to 85 c t stg storage temperature range -55 to +150 c TDA7430 - tda7431 4/21
ps4 22nf ps3 22nf ps2 4.7nf ps1 100nf lp 1.2nf lp1 5.6nf hp1 680nf var-l 2.2 m f hp2 basso-l var-r basso-r recout-l recout-r l-out r-out v s cref 100nf 10 m f 22 m f 220nf r-in4 0.47 m f r-in3 0.47 m f r-in2 0.47 m f dig-gnd scl sda agnd 18nf 2.7k middle-lo middle-li 22nf 18nf 2.7k middle-ro middle-ri 22nf 100nf 5.6k bass-lo bass-li 100nf 100nf 5.6k bass-ro bass-ri 100nf treble-l 5.6nf d95au225b 2.2 m f treble-r 5.6nf lpvc 100nf TDA7430 39 40 9 41 42 43 44 1 18 19 34 14 15 16 17 38 10 11 12 13 27 26 25 24 23 22 21 20 876 32 37 36 35 rearin 2.2 m f rearout 45 r-in1 0.47 m f 33 l-in1 0.47 m f 31 l-in2 0.47 m f 30 l-in3 0.47 m f 29 l-in4 0.47 m f 28 mix 1 m f 32 test circuit (TDA7430) ps4 22nf ps3 22nf ps2 4.7nf ps1 100nf lp 1.2nf lp1 5.6nf hp1 680nf var-l 2.2 m f hp2 basso-l var-r basso-r voutref recout-l recout-r l-out r-out v s cref 100nf 10 m f 22 m f 15k 220nf 220nf 7.5k nbro nbrin r-in 0.47 m f mix 1 m f l-in 0.47 m f 15k 220nf 7.5k nblin nblo 220nf dig-gnd scl sda addr agnd 18nf 2.7k middle-lo middle-li 22nf 18nf 2.7k middle-ro middle-ri 22nf 100nf 5.6k bass-lo bass-li 100nf 100nf 5.6k bass-ro bass-ri 100nf treble-l 5.6nf d95au224b 2.2 m f treble-r 5.6nf lpvc 100nf tda7431 42 1 13 9 2 3 4 5 6 22 23 38 18 19 20 21 41 40 39 34 33 14 15 16 17 32 31 30 29 28 27 26 25 24 12 11 10 8 7 37 36 35 test circuit (tda7431) TDA7430 - tda7431 5/21
electrical characteristics (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w , v in = 1vrms; r g = 600 w , all controls flat (g = 0db), effect ctrl = -6db, mode = off; f = 1khz unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v s supply voltage 7 9 10.2 v i s supply current 10 18 26 ma svr ripple rejection l ch / r ch out , mode = off 60 80 db input stage r in input resistance 35 50 65 k w v cl clipping level thd = 0.3% 2 2.5 vrms c range control range 31.5 db a vmin min. attenuation -1 0 1 db a vmax max. attenuation 31 31.5 32 db a step step resolution 0.5 1 db v dc dc steps adjacent att. step -3 0 3 mv a vo1 voice canceler output 1 l in = r in , r in = on, v mix = 0v fix, 0db attenuation 567db a vo2 voice canceler output 2 l in = r in = 0v v mix = 1v rms fix, 0db attenuation -1 0 1 db a vo3 voice canceler output 3 l in = -r in , v mix = 0v fix, 0db attenuation 567db r lpv low pass filter resistance 22.4 32 41.6 k w r mix input impedance 70 100 130 k w bass control gb control range max. boost/cut +11.5 +14.0 +16.0 db b step step resolution 1 2 3 db r b internal feedback resistance 32 44 56 k w middle control gm control range max. boost/cut +11.5 +14.0 +16.0 db m step step resolution 1 2 3 db r m internal feedback resistance 17.5 25 32.5 k w treble control gt control range max. boost/cut +13.0 +14.0 +15.0 db t step step resolution 1 2 3 db effect control c range control range - 21 - 6 db s step step resolution 0.5 1 1.5 db TDA7430 - tda7431 6/21
electrical characteristics (continued) surround sound matrix test condition (phase resistor selection d0=0, d1=1, d2=0. d3=1, d4=0, d5=1, d6=0, d7=1 symbol parameter test condition min. typ. max. unit g off in-phase gain (off) mode off, input signal of 1khz, 1.4 v p-p , r in ? r out l in ? l out -1 0 1 db d goff lr in-phase gain difference (off) mode off, input signal of 1khz, 1.4 v p-p r in ? r out , l in ? l out -1 0 1 db g mov in-phase gain (movie) movie mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p r in ? r out , l in ? l out 8db d gmov lr in-phase gain difference (movie) movie mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p (r in ? r out ) C (l in ? l out ) 0db g mus in-phase gain (music) music mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p (r in ? r out ), (l in ? l out ) 7db d gmus lr in-phase gain difference (music) music mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p (r in ? r out ) - (l in ? l out ) 0db l mon1 simulated l output 1 simulated mode, effect ctrl = -6db input signal of 250hz, 1.4 v p-p , r in and l in ? l out 4.5 db l mon2 simulated l output 2 simulated mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p , r in and l in ? l out C4.0 db l mon3 simulated l output 3 simulated mode, effect ctrl = -6db input signal of 3.6khz, 1.4 v p-p , r in and l in ? l out 7.0 db r mon1 simulated r output 1 simulated mode, effect ctrl = -6db input signal of 250hz, 1.4 v p-p , r in and l in ? r out C 4.5 db r mon2 simulated r output 2 simulated mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p , r in and l in ? r out 3.8 db r mon3 simulated r output 3 simulated mode, effect ctrl = -6db input signal of 3.6khz, 1.4 v p-p , r in and l in ? r out C 20 db r lp1 low pass filter resistance 7 10 13 k w r hpi high pass filter resistance 42 60 78 k w r lpf lp pin impedance 7 10 13 k w TDA7430 - tda7431 7/21
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit surround sound matrix phase r ps10 phase shifter 1: d1 = 0, d0 = 0 8.3 11.8 15.2 k w r ps11 phase shifter 1: d1 = 0, d0 = 1 10 14.1 18.3 k w r ps12 phase shifter 1: d1 = 1, d0 = 0 12.6 17.9 23.3 k w r ps13 phase shifter 1: d1 = 1, d0 = 1 26.4 37.3 48.85 k w r ps20 phase shifter 2: d3 = 0, d2 = 0 4 5.6 7.2 k w r ps21 phase shifter 2: d3 = 0, d2 = 1 4.8 6.8 8.7 k w r ps22 phase shifter 2: d3 = 1, d2 = 0 6 8.4 10.9 k w r ps23 phase shifter 2: d3 = 1, d2 = 1 12.9 18.3 23.7 k w r ps30 phase shifter 3: d5 = 0, d4 = 0 8.5 12.1 15.6 k w r ps31 phase shifter 3: d5 = 0, d4 = 1 10.2 14.5 18.7 k w r ps32 phase shifter 3: d5 = 1, d4 = 0 12.7 18.1 23.3 k w r ps33 phase shifter 3: d5 = 1, d4 = 1 27.4 39.1 50.75 k w r ps40 phase shifter 4: d7 = 0, d6 = 0 8.5 12.1 15.6 k w r ps41 phase shifter 4: d7 = 0, d6 = 1 10.2 14.5 18.7 k w r ps42 phase shifter 4: d7 = 1, d6 = 0 12.7 18.1 23.3 k w r ps43 phase shifter 4: d7 = 1, d6 = 1 27.4 39.1 50.75 k w speaker & record attenuators c range control range 79 db s step step resolution -0.5 1 1.5 db e a attenuation set error av = 0 to -20db -1.5 0 1.5 db av = -20 to -79db -3 0 2 db v dc dc steps adjacent att. steps -3 0 3 mv a mute output mute condition +70 100 db r vea input impedance 21 30 39 k w audio outputs n o(off) output noise (off) output mute, flat b w = 20hz to 20khz 4 5 m vrms m vrms n o(mov) output noise (movie) mode =movie , b w = 20hz to 20khz 30 m vrms n o(mus) output noise (music) mode = music , b w = 20hz to 20khz, 30 mvrms n o(mon) output noise (simulated) mode = simulated, b w = 20hz to 20khz 30 m vrms d distorsion av = 0 ; v in = 1vrms 0.01 0.1 % s c channel separation 70 90 db v ocl clipping level d = 0.3% 2 2.5 vrms r out output resistance 10 40 70 w v out dc voltage level 3.8 v bus inputs v il input low voltage 1 v v ih input high voltage 3 v i in input current -5 +5 m a v o output voltage sda acknowledge i o = 1.6ma 0.4 v TDA7430 - tda7431 8/21
i 2 c bus interface data transmission from microprocessor to the TDA7430/tda7431 and viceversa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). data validity as shown in fig. 3, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig.4 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tran- sition of the sda line while scl is high. byte format every byte transferred on the sda line must con- tain 8 bits. each byte must be followed by an ac- knowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 5). the peripheral (audioprocessor) that ac- knowledges has to pull-down (low) the sda line during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can gen- erate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio- processor, the m p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 3: data validity on the i 2 cbus figure 4: timing diagram of i 2 cbus f igure 5: acknowledge on the i 2 cbus TDA7430 - tda7431 9/21
software specification interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the TDA7430 /tda7431 address a subaddress bytes a sequence of data (n byte + achnowledge) a stop condition (p) ack = achnowledge s = start p = stop a = address b = auto increment s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au226a b data subaddress data 1 to data n examples no incremental bus the TDA7430 /tda7431 receives a start condi- tion, the correct chip address, a subaddress with the msb = 0 (no incremental bus), n-datas (all these datas concern the subaddress selected), a stop condition. s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au306 0d3 subaddress data xxx d2 d1 d0 incremental bus the TDA7430 /tda7431 receive s a start condi- tion, the correct chip address, a subaddress with the msb = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas subaddress from "1xxx1010" to "1xxx1111" of data are ignored. the data 1 concern thesubaddress sent, and the data 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au307 1d3 subaddress data 1 to data n xxx d2 d1 d0 TDA7430 - tda7431 10/21
msb lsb input attenuation d7 d6 d5 d4 d3 d2 d1 d0 0.5 db steps 000 0 001 -0.5 010 -1 011 -1.5 100 -2 101 -2.5 110 -3 111 -3.5 4 db steps 000 0 001 -4 010 -8 011 -12 100 -16 101 -20 110 -24 111 -28 input attenuation = 0 ~ -31.5db d7 d6 d5 d4 d3 d2 d1 d0 rear switch 0 rearin, rearout pin active 1 no rearin, rearout pin input attenuation selection msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 bxxx00 0 0 input attenuation bxxx00 0 1 surround & out & effect control bxxx00 1 0 phase resistor bxxx00 1 1bass & natural base bxxx01 0 0 middle & treble bxxx01 0 1spe aker attenuation "l" bxxx01 1 0spe aker attenuation "r" bxxx01 1 1 record attenuation "l" bxxx10 0 0 record attenuation"r" bxxx10 0 1 input multiplexer, voice canceller & rec out b = 1 incremental bus; active b = 0 no incremental bus; x = indifferent 0,1 the first byte (subaddress) data bytes address = 80(hex): addr open; 82 (hex): need to connect supply function selection: TDA7430 - tda7431 11/21
msb lsb d7 d6 d5 d4 d3 d2 d1 d0 surround mode 0 0 simulated 0 1 music 1 0 off 1 1 movie out 0 var 1 fix effect control 0000 -6 0001 -7 0010 -8 0011 -9 0100 -10 0101 -11 0110 -12 0111 -13 1000 -14 1001 -15 1010 -16 1011 -17 1100 -18 1101 -19 1110 -20 1111 -21 phase resistor selection msb lsb surround phase resistor d7 d6 d5 d4 d3 d2 d1 d0 phase shift 1 (k w ) 00 12 01 14 10 18 11 37 phase shift 2 (k w ) 00 6 01 7 10 8 11 18 phase shift 3 (k w ) 00 12 01 14 10 18 11 39 phase shift 4 (k w ) 00 12 01 14 10 18 11 39 surround selection TDA7430 - tda7431 12/21
bass selection msb lsb bass d7 d6 d5 d4 d3 d2 d1 d0 2 db steps 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14 natural base 0 nbrin, nbro, nblin, nblo pin active 1 no nbrin, nbro, nblin, nblo pin speaker/record att. r & l selection msb lsb speaker/record att d7 d6 d5 d4 d3 d2 d1 d0 1 db steps 000 0 001 -1 010 -2 011 -3 100 -4 101 -5 110 -6 111 -7 8 db steps 0000 0 0001 -8 0010 -16 0011 -24 0100 -32 0101 -40 0110 -48 0111 -56 1000 -64 1001 -72 mute 101x 11xx x = indifferent 0,1 speaker/record attenuation = 0db ~ -79db TDA7430 - tda7431 13/21
middle & treble selection msb lsb middle d7 d6 d5 d4 d3 d2 d1 d0 2 db steps 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14 treble 2 db steps 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14 TDA7430 - tda7431 14/21
voice canceller/input/recout l & r selection msb lsb d7 d6 d5 d4 d3 d2 d1 d0 voice canceller 0 off 1on input multiplexer 0 0 in2 0 1 in3 1 0 in4 1 1 in1 rec out "l" 0 0 ver 1 (3band) 0 1 ver 2 (surr) 1 0 ver 3 (rear) 1 1 fix rec out "r" 0 0 ver 1 (3band) 0 1 ver 2 (surr) 1 0 ver 3 (rear) 11 fix power on reset bass & middle 2db treble 0db surround & out control+ effect control off + fix + max attenuation speaker/record attenuation l &r mute input attenuation + rearn switch max attenuation + on natural base off voice canceler off input in1 100 w v s d94au204 20 m a gnd pin: l-out, r-out, recout-l, recout-r TDA7430 - tda7431 15/21
20 m a v s 30k vref d95au227 sw gnd pin: ver-l, ver-r, 50k gnd v s v ref d94au200 20 m a pin: l-in, r-in, l-in2, r-in2, l-in3, r-in3, l-in4, r-in4, 10k v s d94au211 20 m a hp1 gnd pin: lp1 20k v s d95au336 20 m a 20k gnd 42k pin: cref 10k 60k gnd v s lp1 hp2 d94au198 pin: hp1 5.5k 60k gnd v s hp1 d94au199 20 m a 5.5k pin: hp2 TDA7430 - tda7431 16/21
20 m a v s 50k vref d95au229 sw gnd pin: rearin 50k v s d95au228a 20 m a gnd gnd pin: addr v s d95au230 20 m a gnd pin: rearout, basso-l, basso-r 20 m a v s 100k vref d94au123 gnd pin: mix d94au205 20 m a gnd pin: scl, sda v s d95au308 20 m a gnd pin: ps1, ps2, ps3, ps4 lp TDA7430 - tda7431 17/21
45k or 25k v s d95au231a 20 m a bass-ro,middle-lo,middle-ro bass-lo gnd : bass : middle pin: bass-li, bass-ri, middle-li, middle-ri, (*) v s d95au232 20 m a bass-li,bass-ri,middle-li,middle-ri gnd (*) 45k : bass 25k : middle pin: bass-lo, bass-ro, middle-lo, middle-ro, 10k v s d95au233a 20 m a gnd gnd pin: vout ref 25k v s d95au309 20 m a gnd pin: treble-l, treble-r vref v s d95au235a gnd pin: nblo, nbro 20 m a v s d95au234 sw gnd pin: nblin, nbrin TDA7430 - tda7431 18/21
sdip42 (0.600") a1 b e b1 d 22 21 42 1 la e1 a2 c e1 e e2 gage plane .015 0,38 e2 e3 e sdip42 dim. mm inch min. typ. max. min. typ. max. a 5.08 0.20 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.38 0.46 0.56 0.0149 0.0181 0.0220 b1 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.60 0.629 e1 12.70 13.72 14.48 0.50 0.540 0.570 e 1.778 0.070 e1 15.24 0.60 e2 18.54 0.730 e3 1.52 0.060 l 2.54 3.30 3.56 0.10 0.130 0.140 outline and mechanical data sdip42 package mechanical data TDA7430 - tda7431 19/21
tqfp44 (10 x 10) dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.014 0.018 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 0.80 0.031 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 3.5?(typ.), 7 (max.) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 outline and mechanical data TDA7430 - tda7431 20/21
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com TDA7430 - tda7431 21/21

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